With advancement in shrinkage and higher integration of semiconductor devices, variation in the threshold voltage of transistors due to statistical fluctuation of channel impurities has become more apparent. The threshold voltage is one of critical parameters which determine performances of the transistors. In order to manufacture the semiconductor devices with high performance and high reliability, it is important to reduce the variation in the threshold voltage due to the statistical fluctuation of impurity.
As one technique of reducing the variation in the threshold voltage due to the statistical fluctuation of impurity, there has been proposed a transistor structure called DDC transistor (Deeply Depleted Channel transistor). The DDC transistor is configured by a high-concentration channel impurity layer having a sharp distribution of impurity concentration, and a non-doped, epitaxially-grown silicon layer forced thereon.
Patent Document 1: Japanese Laid-open Patent Publication No. S62-179142
Patent Document 2: Japanese Laid-open Patent Publication No. H10-335679
Patent Document 3: Japanese Laid-open Patent Publication No. 2012-174878
The transistors having the DDC structure are very effective in terms to suppressing the variation in the threshold voltage due to the statistical fluctuation of impurity, but cannot suppress variation in the threshold voltage typically due to gate length which fluctuates from chip to chip. For low voltage operation of the transistors, it is necessary to suppress both types of variations in the threshold voltage. While the transistors having the DDC structure are effectively corrected in the inter-chip fluctuation by applying a back bias, this makes a voltage to be applied to the veil different frost a source voltage and a reference voltage, so that the latch-up immunity may degrade due to noise induced by inverted voltage.